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$xhtml = array(
	'<{title}>' => '...',
	'takedown' => '2017-11-01',
	'<{body}>' => <<<END
<section id="general">
	<h2>General news</h2>
	<p>
		I have nothing to say today.
		Sorry.
	</p>
</section>
<section id="university">
	<h2>University life</h2>
	<p>
		I wrote up my discussion post on data flip-flop gates and D-latches:
	</p>
	<blockquote>
		<h4>D-latches</h4>
		<p>
			The book did not go into how to build a data flip-flop gate, which I found to be a pain, especially considering that it taunted us with the fact that it <strong>*could*</strong> be built with regular, non-sequential logic gates; nand gates, in particular.
			We were given nothing to go off to help us figure out how to build them.
			For anyone interested, I looked up a solution that wasn&apos;t quite what we were doing, then modified it to match what the textbook described.
		</p>
		<img src="/img/CC_BY-SA_4.0/y.st./coursework/CS1104/D-latch.png" alt="D-latch gate composed of nand gates" class="framed-centred-image" width="248" height="132"/>
		<p>
			If you try playing with this one in Logisim, keep in mind that Logisim recalculate the state of all your wires in certain situations (such as when moving gates and wires around) and it doesn&apos;t like oscillation (flipping back and forth.
			If Logisim recalculates the wire states, it&apos;ll lock up in an error state.
			There doesn&apos;t seem to be a way to recover from this, even if you change around your wires to fix the problem.
			Just save your project, close it, and reopen it.
			You&apos;ll have a different error; turn the clock input on, and the error will resolve.
			Additionally, the oscillation error won&apos;t occur in the first place if the clock is on (as that allows the output to flex), so try to keep the clock on when you&apos;re moving wires around if you want to modify this.
		</p>
		<p>
			From the looks of it, the gates on the right are in a partial feedback loop; their inputs from the left, if opposite, determine which gate is outputting which value.
			However, if both inputs to this pair are both <code>1</code>, they&apos;re irrelevant, and the two gates hold each other&apos;s output stable using their own output.
			This seems to be because <code>1</code> nand <code>1</code> from one gate will remain outputting <code>0</code>, and both <code>1</code> nand <code>0</code> and <code>0</code> nand <code>0</code> will output <code>1</code>.
			The two inputs to this pair will never both be <code>0</code>, but if they were, it&apos;d make the output always <code>1</code>; the balance between the two would be lost, as they&apos;d statelessly receive a <code>0</code> bit, and it only takes one <code>0</code> to ensure the output of a nand gate is <code>1</code>.
			So the goal, it seems, is to ensure the two inputs can never both be <code>1</code>
			at the same time.
		</p>
		<p>
			We can do that by inverting the input of one of the right two nand gates.
			From the looks of it, we can invert the data input on either of the left-most gates; it doesn&apos;t really matter.
			The point is that there are four possible input combinations, and only one makes a nand gate output <code>0</code>.
			What we&apos;re trying to do is cause the case in which one gate will output <code>0</code> to be misaligned from the case the other will output <code>0</code>.
			It has to be the data bit that gets inverted before entering one of the gates though, not the clock bit.
			If you instead invert the clock bit, it acts like a data bit while the data bit acts like a clock bit.
			I think this is because the data bit needs to be opposite on both of the leftmost nand gates to flip the polarity of their combined input; the data bit needs to be able to ensure that a particular one of the pair outputs <code>1</code>, regardless of what the clock bit is doing.
			The clock bit, on the other hand, only had to ensure that both of the leftmost nand gates are outputting <code>1</code> by feeding both gates <code>0</code>.
			It makes the data bit irrelevant, as any input nanded with <code>0</code> will result in an output of <code>1</code>.
			Finally, once you have the loop gate working, add the output pin to whichever of the rightmost nand gates is outputting the bit you were trying to store.
			The two are always inverses, and which wire has the bit you want will be determined by which gate you inverted the data input of.
		</p>
		<p>
			If you don&apos;t understand all that, don&apos;t feel too bad.
			I&apos;m really only able to understand it a piece at a time, and once I try to figure out the next piece, I forget why the piece I figured out before works.
			Still, I thought it would be nice to have at least <strong>*some*</strong> sort of explanation as to how a stateful gate such as a data flip-flop works.
			The original, unmodified design I found can be found at <a href="http://learningaboutelectronics.com/Articles/D-flip-flop-circuit-with-NAND-gates.php"><code>http://learningaboutelectronics.com/Articles/D-flip-flop-circuit-with-NAND-gates.php</code></a>.
			The page doesn&apos;t explain <strong>*why*</strong> it works though, and the gates they show there have two outputs instead of one.
		</p>
		<h4>Data flip-flops</h4>
		<p>
			The textbook explains that a data flip-flop stores a value, always outputting the value stored during the previous clock cycle.
			Each clock cycle, it stores a new value and outputs the old one.
			It takes two inputs: the clock bit and the data bit; it has one output: the current internal state (Nisan &amp; Schocken, n.d.).
			Several sources seem to say that data flip-flops output both the stored value and the inverse though, so it probably varies by the implementation.
		</p>
		<p>
			The D-latch described in the discussion assignment seems identical except for one key trait: it has an open state and closed state.
			If the D-latch is open, it takes the new value supplied to it, otherwise, it doesn&apos;t.
			That sounds ... exactly like the circuit above and the one I modified to get it.
			It turns out that circuit&apos;s not a data flip-flop at all, but a D-latch, despite the page that talked about it saying otherwise.
			On the other hand, a data flip-flop only changes state right when the clock cycle begins.
			(It&apos;s not open for half the cycle like a D-latch is.)
		</p>
		<p>
			So how do we build one from the other?
			Let&apos;s start with building the data flip-flop from the D-latch, since we have a D-latch and not a data flip-flop.
			The first answer I came up with is to try to prevent the clock bit from changing throughout the cycle.
			The D-latch provides constant output, so why not chain two together?
			That didn&apos;t pan out though.
			The clock bit isn&apos;t the volatile one.
			Somehow, we have to prevent the <strong>*data*</strong> bit from changing, except right when the clock strikes.
			Why not chain two D-latches together that way instead?
			We can use the output of one D-latch as input to the data input pin of the other.
			From there, we can alternate which D-latch is in the open state, so the data bit only fully propagates once per cycle.
		</p>
		<img src="/img/CC_BY-SA_4.0/y.st./coursework/CS1104/data_flip-flop.png" alt="Data flip-flop gate composed of nand gates" class="framed-centred-image" width="450" height="138"/>
		<p>
			As you can see, the left D-latch doesn&apos;t have an inverted output bit, but that&apos;s fine.
			If you&apos;re working with a D-latch that has both output bits, you&apos;ll need to throw out the inverted output bit or wire it to something that it won&apos;t actually have any effect on.
			(For example, pipe it through a not gate and use an and gate to combine it with the non-inverted output bit; but why do that when you can just throw out the unneeded data more efficiently?)
		</p>
		<p>
			The book thought it would be a good idea to just skip over how these are implemented, but had I not gone out to find how to implement this basic building block, I wouldn&apos;t have understood it well enough to build something bigger from it.
		</p>
		<p>
			Now that we have actual data flip-flops, how do we build D-latches from them?
			I&apos;m not sure we honestly need to.
			D-latches are a simpler component than data flip-flops, and building simple components out of complex components is just begging to have a convoluted mess.As a thought experiment, I tried to figure out how to build D-latches from data flip-flops anyway, but I couldn&apos;t come up with a working design.
			The fact is that the D-latch needs to be able to constantly listen to the data bit when the latch is open, but a data flip-flop isn&apos;t able to provide that.
			This seems like an impossible task to me.
		</p>
		<p>
			I don&apos;t think the book&apos;s kidding when it says all logic gates can be implemented with a series of nand gates.
			Even sequential logic is completely buildable using these versatile gates.
		</p>
		<div class="APA_references">
			<h4>References:</h4>
			<p>
				Nisan &amp; Schocken. (n.d.). Sequential Logic. Retrieved from <a href="https://my.uopeople.edu/mod/resource/view.php?id=132831"><code>https://my.uopeople.edu/mod/resource/view.php?id=132831</code></a>
			</p>
		</div>
	</blockquote>
</section>
END
);
